The average time interval between a storage peripheral (usually a disk drive or semiconductor memory) receiving a request to read or write a certain location and returning the value read or completing the write.
The area of the RAM that stores the bits. The array consists of rows and columns, with a cell at each intersection that can store a bit. The large rectangular section in the centre of the die where the memory is stored.
A process in a multitasking system whose execution can proceed independently in the background.
Memory that is not synchronized with the system clock. EDO and FPM are examples of asynchronous memory.
A synchronous DRAM feature that allows the memory chip's circuitry to close a page automatically at the end of a burst.
Ball Grid Array (BGA)
A type of memory chip with solder balls on the underside for mounting. Use of BGA allows die package size to be reduced because there is more surface area for attachment. Smaller packaging allows more components to be mounted on a module, making greater densities available. The smaller package also improves heat dissipation for better performance. See CSP and FBGA.
The capacity to move data on an electronic line such as a bus or a channel. In short, the amount of data moved relative to a specific time frame.
A slot or group of slots that must be populated with modules of like capacity in order to fulfill the data width requirement of the CPU
Burst EDO is a variant on EDO DRAM in which read or write cycles are batched in bursts of four. Burst EDO bus speeds range from 40MHz to 66MHz, as opposed to the 33MHz bus speeds that can be accomplished using fast page mode or EDO DRAM.
Numbering system based on two digits: 0 and 1.
Basic input/output system. Often referred to as CMOS, the BIOS provides an interface for a computer's hardware and software. The BIOS configuration determines how your hardware is accessed.
Binary digit. The smallest piece of data (a 1 or a 0) that a computer recognizes.
A physical unit of information in a logical record. Block size is usually expressed in bytes.
A circuit or system drawing concerned with major functions and interconnections between functions.
A buffer isolates the memory from the controller to minimize the load on the chip set. It is typically used when the system has a high density of memory and/or when a system has more than 3 memory module sockets.
The process of exercising an integrated circuit at elevated voltage and temperature. This process accelerates failures normally seen as "infant mortality" in a chip. (Those chips that would fail early during actual usage will fail during burn-in. Those that pass have a life expectancy much greater than that required for normal usage.)
Circuitry that is used to move data.
A single transaction between system memory and the CPU.
A series of 8 bits.
Column address strobe is the signal which tells the DRAM to accept the given address as a column address. It is used with RAS and a row address to select a bit within the DRAM.
CAS before RAS. Column address strobe before row address strobe. A refresh technique in which the DRAM keeps track of the next row it needs to refresh.
A small, fast memory holding recently accessed data, designed to speed up subsequent access to the same data. Typically used between a processor and main memory.
The property of a circuit element that allows it to store an electrical charge.
Extra data bits provided by a module to support ECC function.
Complex Instruction Set COmputing. This design logic is usually associated with microprocessirs. CISC chips use instructions or commands, that involve several steps in one.
The number of pulses emitted from a computer's clock in one second. It determines the rate at which logical or arithmetic gating is performed in a synchronous computer.
Complementary Metal Oxide Semiconductor. A process that uses both N- and P-channel devices in a complimentary fashion to achive small geometries and low power consumption. On a PC CMOS generally refers to the BIOS information stored on a CMOS chip.
Cache on a stick. Coast modules are used to upgrade a motherboard's L2 cache and Tag memory on some socket 7 and older motherboards.
Chip on board. A system in which semiconductor dice are mounted directly on a PC board and connected with bonded wires or solder bumps. The dice are usually mechanically protected with epoxy.
Part of the memory array. A bit can be stored where a column and a row intersect.
A small flash memory module. The memory chips are enclosed in a plastic ase and retain data after they are removed from the system. The most common uses for these are in pagers, handheld computers, cell phones, digital cameras, and audio players.
One of the major units in a computer that interprets and carries out the instructions in a program.
Central processing unit. The computer chip primarily responsible for executing instructions.
Double data rate is a type of SDRAM in which data is sent on both the rising and falling edges of clock cycles in a data burst. It is usually referred to as DDR as opposed to DDR SDRAM.
An individual rectangular pattern on a wafer that contains circuitry to perform a specific function. Die are encapsulated to form the black chips that are then placed on a module.
Dual inline memory module. A module with signal and power pins on both sides of the board (front and back).
A computer memory address that is included as part of the instruction.
Direct memory access
A computer feature that allows peripheral systems to access the memory for both read and write operations withour affecting the state of the computer's central processor.
Systems using intelligent input/output controllers and direct - memory - access control to free the CPU of the details of block transfers.
Dynamic random access memory. A type of memory component used to store information in a computer system. "Dynamic" means the DRAMs need a constant "refresh" (pulse of current through all of the memory cells) to keep the stored information. (See also RAM and SRAM.)
A memory module with two banks or rows.
Type of RAM (random access memory). To keep data in the DRAM, this data needs to be "refreshed" (recharged). The electric charge fades out of a DRAM like air seeps out of a balloon. Because of this change, it is called dynamic.
Electronically Erasable PROM.
Electronically Alterable Read-Only Memory.
Error correcting code. Logic designed to detect and correct memory errors.
Extended data out. An asynchronous DRAM operating mode that improves access times compared to fast page mode (FPM) DRAMs.
Electronically Erasable Programmable Logic Device.
Electrically erasable, programmable, read-only memory. EEPROMs differ from DRAMs in that the memory is saved even if electrical power is lost. Additionally, the memory can be erased and reprogrammed repeatedly.
Electrostatic Discharge (ESD)
The dissipation of electricity. (In layman's terms, a "shock.") ESD can easily destroy semiconductor products, even when the discharge is to small to be felt.
A local area network allowing several computers to transfer data over a communications cable.
Fine pitch ball grid array is a die package with a fine pitch ball arrangement on the underside of the package (larger than CSP).
Failures In Time.
Fast page mode - A feature used to support faster sequential access to DRAM by allowing multiple accesses to the currently open row to be made after supplying the row address just once.
A small flash memory module. The memory chips are enclosed in a plastic case and retain data after they are removed from the system. The most common uses for these are in laptops, pagers, handheld computers, cell phones, digital cameras, and audio players. There are several different form factors of flash cards, including Compact Flash, SmartMedia, PCMCIA, and Small Form Factor Flash Card.
Flash memory is a non-volatile memory device that retains its data after the power is removed.
A circuit with two stable states that can be changed form on eto the other. Flio-flops are the storage element in most of the SRAMs.
Amount of memory equal to 1024 Megabits (1,073,741,824 bits) of information. Abbreviated Gb.
Amount of memory equal to 1024 Megabytes (1,073,741,824 bytes) of information. Abbreviated GB.
Hyper page mode, also known as EDO.
High Temperature Operating Life.
Connection to a CPU that provides a data path between the CPU and external devices, such as a keyboard, display, or reader. It may provide input only, output only, or both input and output.
Integrated circuit. A tiny complex of electronic components and their connections that is produced in or on a small slice of material (such as silicon).
In circuit Emulator.
Identification Detect. Pins present on DIMMs to provide informtion to the system using the module.
Joint Electron Device Engineering Council. The group that establishes the industry standards for memory operation, features, and packaging.
Notches on a memory module that help prevent it from being installed incorrectly or into an incompatible system.
Approximately on ethousand bits: 1 bit x 210 (that is 1,024 bits).
A unit of measurement approximately equal to 1024 bytes.
Level 1 cache. A small cache integrated in a processor that provides quick access to the most recently used data.
Level 2 cache. L2 cache has the same purpose as L1 cache, but is usually not integrated into the processor. L2 cache is traditionally made of SRAM and in socket 7 and older motherboards was in some cases upgradeable. See COAST.
Latency (also called CAS Latency)
The amount of time in nanoseconds (often measured in clock cycles) between a request to read the memory, and when it is actually output. SDRAMs are typically referred to as CL2 or CL3, with CL2 parts being faster.
Amount of memory equal to 1,048,576 bits of information. (Abbreviated Mb.)
Amount of memory equal to 1,048,576 bytes of information. (Abbreviated MB.)
A measurement of clock cycles in millions of cycles per second.
The amount of memory in an IC and how it is accessed.
Minimum amount of time required for a memory to complete a cycle such as read, write, read/write, or read/modify/write.
The logic chip used to handle the I/O (input/output) of data going to and from memory. See Chipset.
Cache: static random access memory containing recently used information
DRAM: dynamic random access memory.
DDR SDRAM: double data rate synchronous dynamic random access memory. Usually referred to as DDR.
RAM: random access memory.
RDRAM: Rambus dynamic random access memory.
ROM: read only memory (permanent memory that cannot be changed).
SDRAM: single data rate synchronous dynamic random access memory.
SLDRAM: synchronous link dynamic random access memory.
SRAM: static random access memory.
A unit of measure equivalent to one-millionth of a meter; synonymous with micrometer.
Millions of instructions per second. This measurement is generally used when describing the speed of computer systems.
The main printed circuit board in a computer that carries the system buses. It is equipped with sockets to which all processors, memory modules, plug-in cards, daughterboards, or peripheral devices are connected.
Mean Time Between Failures.
Mean Time To Failures.
Memory unit. Usually a printed circuit board assembly populated with memory chips that stores a certain quantity of memory. Intel term for one of the types of cards in a memory system card set.
One billionth of a meter.
One billionth of a second; used to measure the speed of the parts
Usually 4 bits or half a byte.
A memory that retains information if power is removed and then reapplied.
Software controlling the overall operation of a multipurpose computer system, including such tasks as memory allocation, input and output distribution, interrupt processing, and job scheduling.
Programmable Array Logic. A device that can be programmed to do certain logic functions. Then a fuse inside of the device can be blown so the programmed information can never be changed.
The number of bits that can be accessed from one row address. This is also sometimes referred to as a row.
Mode in which if RAS is kept low and the DRAM is given a column address without being given a new row-address, the chip will remember which row it was on the last time and automatically stay on that row. It is like saying that all the bits along one row are all on the same page, and the part will assume the same page is intended until a different page is specified.
A bit added to a group of bits to detect the presence of an error. The parity bit looks at the other 8 bits and determines if they are even or odd and correspondingly is a 0 or 1. The system compares the 8 bits with the parity bit. If they both are even or odd, the data is assumed to be correct. If one is even and one is odd, there is an error, and typically the system will fail.
Printed circuit board. Board that contains layers of circuitry that is used to connect components to a system.
The PC100 specification defines the requirements for SDRAM modules used on 100MHz FSB motherboards.
The PC133 specification details the requirements for SDRAM modules used on 133MHz FSB motherboards. PC133 SDRAM can be used on 100MHz FSB motherboards but will not yield a performance advantage over PC100 memory at 100MHz.
Personal Computer Memory Card International Association. An industry organization that helps to set standards for flash cards.
Circuitry on certain memory modules that provides information to the system.
Cache that is closest to the processor: typically located inside the CPU chip. Can be implemented either as a unified cache or as separate sections for instructions and data.
A device or method used to keep the output voltage of a device at a high level, often a resistor network connected to a positive supply voltage.
Quad Flat Pack (QFP)
A flat, rectangular, integrated circuit with its leads projecting from all four sides of the package without radius.
Random access memory. A data storage device for which the order of access to different locations does not affect the speed of access, except for bursts. Data is typically stored in RAM temporarily for use by the process or while the computer is operating. FPM, EDO, SDRAM, DDR, etc. are all types of RAM.
Row address strobe. The signal that tells the DRAM to accept the given address as a row address. Used with CAS and a column address to select a bit within the DRAM.
The amount of time required for the output data to become valid once the read and address inputs have been enabled. Generally called access time.
The process used to restore the charge in DRAM cells at specific intervals.
A count of the number of rows (in thousands) refreshed at a time in a refresh cycle. Common refresh rates are 1K, 2K, 4K, and 8K.
Registers delay memory information for one clock cycle to ensure all communication from the chipset is collected by the clock edge, providing a controlled delay on heavily loaded memories.
An identifier that indicates the position of a memory location in a computer routine relative to the base address as opposed to the memory location's absolute address.
The amount of time must remain stable after a device or circuit has been clocked: also called hold time.
Rambus DRAM is a revolutionary type of DRAM that uses a 16-18 bit data path and is designed to operate with FSB speed of 800MHz, producing a burst transfer rate of 1.6 gigahertz.
Rambus inline memory modules used for Rambus DRAM.
Reduced Instruction Set Computing. The design methodology is usually associated with microprocessors. RISC chips use simpler instructions, or commands, than CISC chips. However, they need to use more steps to perform many functions that CISC chips perform in one step.
The amount of time required for a signal level change to icrease from ten percent to ninety percent of its final specified value.
Part of the RAM array; a bit can be stored where a column and a row intersect. Sometimes also referred to as a page.
Serial Presence Detect
An EEPROM on certain memory modules used to store and provide information to the system using the module.
Synchronous dynamic random access memory delivers bursts of data at high speeds using a synchronous interface.
Synchronous graphics RAM. A single port DRAM designed for graphics hardware that requires high-speed throughput such as 3-D rendering and full-motion video.
A reduction in die (chip) size. A reduction in the size of the circuit design resulting in smaller die sizes that increases the number of possible die per wafer.
Single inline module. Same as SIP except with a connector edge instead of leads.
Single inline memory module. A high-density DRAM package alternative consisting of several components connected to a single printed circuit board.
A memory module with only one bank or row.
Single inline package. A component or module that has one row of leads along one side.
Synchronous link dynamic random access memory. SLDRAM is a type of SDRAM that uses a multiplexed command bus allowing fewer pins to increase bandwidth and allow higher FSB speeds.
Small outline dual inline memory module. Smaller and thinner than standard DIMMs, SODIMMs are typically used in laptop computers.
Small outline Rambus inline memory module. SORIMMs have a smaller profile that standard RIMMs and are used in laptop computers and systems that have strict size requirements.
Small outline J-lead package. A rectangular package with leads sticking out of the side of the package. The leads are formed in a J-bend profile, bending underneath and towards the bottom of the package.
An error caused by a temporary disruption of the memory cell.
The time it takes to put information into memory or get information out of memory. It is measured from the time that an address and proper control signals are given, until the information is stored or placed in the device's output(s). RAM speed is typically expressed in nanoseconds (lower is faster) for EDO and FPM, and in MHz (higher is faster) for SDR SDRAM, DDR, SDRAM, and RDRAM.
Solid State Disk - Storage unit without moving parts. Built of Semi-Conductor chips ( Nand Flash (non volatile) or DRAM (volatile))
Smallest or lowest address that a memory system will respond to.
Static Random Access Memory (SRAM)
An integrated circuit similar to a DRAM with the exception that the memory does not need to be refreshed. Unlike volatile memory (ie, DRAM), SRAM retains its contents even when the main current is turned off.
Memory that has its signals synchronized with the system clock. SDRAM and DDR are examples of synchronous memory types.
TAG memory acts as an index for the information stored in L2 cache. It is usually composed of SRAM.
Thin small outline package. It is thinner and slightly smaller than an SOJ, with gullwing-shaped leads. A thin, rectangular package with leads sticking out the sides of the package.
This is where the chip set controller deals directly with the memory. There is nothing between the chip set and the memory chips on the module as they communicate.
A micron (or micrometer). A unit of length equal to one millionth of a meter.
A microsecond: One millionth of a second.
Collector Common Voltage.
Video RAM. DRAM with an on-board serial register/serial access memory designed for video applications.
This is system memory that is simulated by the hard drive. When all the RAM is being used (for example if there are many programs open at the same time) the computer will swap data to the hard drive and back to give the impression that there is slightly more memory.
Write Enable. WE muct be pulsed low when data is written to the chip.
Time expended from the moment data is entered for storage to the time it is actually stored in the memory cell.
An addressing mode in which the address is given as an unsigned binary number that specfies one of the memory locations between 0 and 256.